Flip-chip bonder

Tampere University Foundation sr ('TAU') is inviting tenders for 'Flip-chip bonder'. A die bonder for mounting optoelectronic components epilayer structure down on substrates having pre-deposited Indium or eutectic (Gold-rich) AuSn solder. System must have at least passive alignment tools (i.e., the system does not need to utilize the light emitting or absorbing property of the components in the component alignment stage). System should based on an open platform in hardware and software level to enable TAU to further develop new processes. Moreover, system should enable to use it in a manual operation mode as well as automating a part or the complete process flow.

Tampere University is procuring a system that enables: - flip-chip-bond optoelectronic devices such as laser diodes, superluminescent diodes or solar cells on different substrates including metallized ceramics and photonic integrated circuits. - flip-chip-bond IC-chips or chiplets to interposers towards 2.5D and 3D integration with anisotropic conductive paste (ACP). Optoelectronics: The system will be employed in the research of high-performance semiconductor devices to create high precision, reliable, and reproducible bonding processes between relatively sensitive edge and surface light-emitting semiconductor chips and substrates using pre-deposited solder materials (such as Indium and eutectic gold-tin solders) The devices (~100um thick) are mounted epilayer side (~1-3um thick) down without any vertical side insulation on the solder material. Therefore, it is challenging to avoid electrically short circuiting the chip. Moreover, good mechanical bond strength and high thermal conductivity over the bond are the main targets of an acceptable bond. In the procurement, the bond quality and reliability are preferred over the throughput. Critical characteristics are also a user-friendly and intuitive user interface, enabling simple use of the system and effective process development. System-on-Chip (SOC): SoC circuits are integrated circuits with distributed multi-chip functional layout. TAU develops SoCs with fabless approach in collaboration with state-of-the-art semiconductor technology allowing micro-bumps down to 40 µm pitch. Hybrid integration process is based on use of interposer chips and Au, In and Cu based thermo-sonic-compression bonding and ACP. System will be employed in research of SoC architectures including 3D integration towards chip stacking, testing of different integration strategies and towards making SoC-demonstrators. Budget is not going to be extended over 470 000 € (covering all mandatory requirements and tendered options). Procurement is funded directly by Business Finland - and indirectly by EU RRF Regulation (EU 2021/241 Recovery and Resilience Facility). PHASING OF THE CALL: Tender is divided in two parts: - In phase one, accepted quotations are graded and up to 95 points are rewarded from quotation and related paperwork. - In second phase, additional 80 points are awarded (totaling as max 175 points) to tenderers based on evaluation tests done with demo system provided by tenderer. Only two (2) tenderers who have achieved most points in phase one are to be invited to phase 2. If tenderer is not within best two (2) in phase 2 but is within five (5) points from 2nd place this tenderer is invited to phase 2. If tenderers are evaluated to have equal merit in some evaluation criteria all tenderers receive same number of points as they would in case where only one tenderer would meet criteria. For example, in point category where winner receives 10 points, all equal winners get 10 points. TAU reserves right to visit tenderers after closing of tender to evaluate ease of use and other aspects relevant for selection. Tenderer must have demo system prepared for this within two (2) months from closing of tender.

Contracting authority (Tampere University Foundation sr) has fixed date deadlines for notice.